An Activity Detection System for Frequency - Encoded Pixels

It is possible, using a first-order sigma-delta modulation scheme, to represent an imager's pixel value as an oversampled bit stream. The goal of the project was to demonstrate the feasibility of computer vision algorithms on such sigma-delta encoded bit streams. The computational modules used were constrained to fit within the footprint of a single pixel. This ensures that fully parallel operation could be achieved using a 3D architecture. 3D silicon technology allows multiple wafers to be stacked together and interconnects to be made between adjacent layers. Bonding wafers together in this manner would allow computational modules to be placed directly beneath its associated pixel. This process increases the potential for high parallelism and low power computation. The activity detection algorithm which was developed incorporates a frequency-locking analog storage mechanism with a lowpass filter/monitor to simulate a multimodal adaptive background activity detector. This system has been simulated in software and has proven itself capable of detecting activity with a fixed field of view. The simulation was developed for the TI TMS320C40 DSP and later extended to an x86 architecture for faster performance and real time evaluation. The GoDSPTM Code Composer IDE was used to develop the DSP software while running it on a White Mountain DSP Slalom-40 board. The x86 implementation was written using MVC++-4.0 running on a 450 Mhz Pentium II based Gateway GP6-450. Thesis Supervisor: Lisa McIlrath Title: Visiting Professor, MIT Al Laboratory